1. Field of the Invention
The present invention relates to a driver for a display panel and an image display apparatus that employ an organic light-emitting diode (OLED), and more particularly to a driver for a display panel and an image display apparatus that can prevent generation of uneven luminance and allow space saving.
2. Description of the Related Art
Along with the growing popularity of mobile computing, demand for flat-type displays is increasing. Commonly used flat-type display is a liquid crystal display, which however is not immune to problems such as a narrow viewing angle and unfavorable response characteristics.
In recent years, image displays employing OLEDs have attracted attentions as flat-type image displays with a wide viewing angle and good response characteristics. The OLED recombines positive holes and electrons injected into a light emitting layer to emit light.
Such conventional image display apparatus includes, for example, a plurality of pixel circuits arranged in a matrix, a signal line driving circuit that supplies a luminance signal described later via plural signal lines to the plurality of pixel circuits, and a scan line driving circuit that supplies a scanning signal to the pixel circuits for selection of a pixel circuit to which the luminance signal is to be supplied via plural scan lines.
FIG. 8 is a block diagram of a structure of a conventional image display apparatus. The image display apparatus shown in FIG. 8 includes an organic electroluminescent (EL) panel 1, a controller 2, a gate driver 3, a drain driver 4, and a common driver 5. A pixel circuit in the organic EL panel 1 is, as shown by an equivalent circuit diagram in FIG. 8, formed with an OLED 6, a driving transistor 7, a selecting transistor 8, and a capacitor Cp, and the pixel circuits are arranged like a matrix.
The OLED 6 is a light emitting device that emits light when a voltage equal to or higher than a level of a threshold is applied between an anode and a cathode. With the application of the voltage equal to or higher than the threshold between the anode and the cathode of the OLED 6, electric currents flow through an organic EL layer to make the OLED 6 emit light. The anode of the OLED 6 is connected to a common line CL provided for each row (i.e., horizontal direction in the drawing) of the organic EL panel 1.
The driving transistor 7 is formed from an n-channel thin film transistor (TFT). A gate of the driving transistor 7 is connected to a source of the selecting transistor 8. Further, a drain of the driving transistor 7 is connected to the cathode electrode of the OLED 6. Further, a source of the driving transistor 7 is connected to the ground (0V).
The driving transistor 7 serves to switch over an ON state and an OFF state of the power supplied to the OLED 6. The gate of the driving transistor 7 retains a driving signal supplied from the drain driver 4 described later.
The driving transistor 7 has characteristics that an on-resistance attains a sufficiently lower level than resistance of the OLED 6 (e.g., not more than one tenth), and an off resistance attains a sufficiently higher level than the resistance of the OLED 6 (e.g., not less than ten times) when a common signal is applied to the OLED 6 by the common driver 5 described later. Hence, when the driving transistor 7 is ON, most of the voltage output from the common driver 5 is divided and supplied to the OLED 6, whereby the OLED 6 emits light with substantially the same intensity regardless of the fluctuation in characteristics of the driving transistors 7.
On the other hand, when the driving transistor 7 is OFF, most of the voltage output from the common driver 5 is divided and supplied between the source and the drain of the driving transistor 7, and the OLED 6 does not receive a voltage of a level equal to or higher than the threshold, whereby the OLED 6 does not emit light.
The selecting transistor 8 is formed from an n-channel TFT. The gate of the selecting transistor 8 is connected to a gate line GL provided for each row (arranged along the horizontal direction in the drawing) in the organic EL panel 1, whereas the drain of the selecting transistor 8 is connected to a drain line DL provided for each column (arranged along the vertical direction in the drawing) in the organic EL panel 1. Further, the source of the selecting transistor 8 is connected to the gate of the driving transistor 7. The selecting transistor 8 serves to switch over between an ON state and an OFF state of the supply of the driving signal to the gate of the driving transistor 7 from the drain driver 4 described later.
The capacitor Cp retains the driving signal supplied from the drain driver 4 described later for at least one sub field time period. The driving signal retained by the capacitor Cp is used for switching over of the driving transistor 7 between ON and OFF. The capacitor Cp and the driving transistor 7 together form a switch to cause the OLED 6 to emit light.
The gate driver 3 outputs selection signals X1 to Xn according to a gate control signal GCONT supplied from the controller 2. Only one of the selection signals X1 to Xn is rendered active at one timing to select a gate line GL in the organic EL panel 1. Thus, the selection signal is supplied to the gate of the selecting transistor 8 connected to the selected gate line GL, whereby the selecting transistor 8 is turned ON.
The drain driver 4 includes a shift register, a latch circuit, and a level converter. In the shift register, one (i.e., a logic “high”) is set as an initial bit in response to a start signal contained in a drain control signal DCONT supplied from the controller 2, and the bit shift occurs at every receipt of a shift signal in the drain control signal DCONT.
The latch circuit is formed from plural latch circuits of the number corresponding to the number of the bits of the shift register. A latch circuit, which corresponds to the bit to which “one” is set in the shift register, latches a light emission signal IMG supplied from the controller 2. When the light emission signals IMG for one row in one subfield are latched in the latch circuit, in response to a switching signal in the drain control signal DCONT, the latched light emission signals IMG are shifted and latched by the latch circuit in the next stage. Then, the latch circuit continues to latch the light emission signals IMG for the next row.
The level converter outputs driving signals Y1 to Yn of a predetermined voltage corresponding to the light emission signals IMG latched by the latch circuit to the drain lines DL of the organic EL panel 1 according to an output enable signal in the drain control signal DCONT. Each of the driving signals Y1 to Yn supplied from the level converter is accumulated on the gate of the driving transistor 7 and turns the driving transistor 7 ON.
The common driver 5 generates common signals Z1 to Zn to be applied to the anode electrodes of the OLED 6 based on a common control signal CCONT supplied from the controller 2. Each of the common signals Z1 to Zn takes one of two values, i.e., ON or OFF, and is applied to the anode electrodes of the OLED 6 of each row via the common line CL. Thus applied ON voltage is sufficiently higher than the level of the threshold voltage of the OLED 6.
Here, the common signals Z1 to Zn are power source voltages supplied to the OLED 6 and have a higher level than the voltage levels of the selection signals X1 to Xn and the driving signals Y1 to Yn. Hence, if the lines are to be identified according to the voltage levels thereof, the common line CL can be labeled as a power source line, whereas the gate line GL and the drain line DL are labeled as control lines.
When the driving transistor 7 is ON, a voltage of a level to cause saturation of the emission luminance of the OLED 6 is applied between the anode electrode and the cathode electrode of the OLED 6. On the other hand, when the driving transistor 7 is OFF, the voltage to be applied between the anode electrode and the cathode electrode of the OLED 6 attains a lower level than the threshold voltage of the OLED 6 since most of the voltages of the common signals Z1 to Zn are divided and supplied to the driving transistors 7.
Here, plural pads (corresponding to terminals) are provided for the gate lines GL, the drain lines DL, and the common lines CL in the gate driver 3, the drain driver 4, and the common driver 5, respectively. Each pad is electrically connected to the corresponding gate line GL, drain line DL, or common line CL.
Further, an amount of electric current flowing through the common line CL which serves as the power source line is larger than the amount of electric current flowing through the gate line GL or the drain line DL that serve as the control lines. Hence, the pad for the common driver 5 (i.e., the pad connected to the power source line) needs to be larger in area than the pad for the gate driver 3 or the drain driver 4 (i.e., the pad connected to the control line) to ease the influence of the large electric current.
Such conventional device is disclosed in Japanese Patent Application Laid-Open No. 10-333641.
In the conventional image display apparatus, however, together with the increase in the size of the organic EL panel 1, the wirings such as the common line CL, the gate line GL, and the drain line DL become longer to increase the wiring resistance. In particular, since the voltage level of the common signals Z1 to Zn is relatively high compared with signals supplied via the gate line GL and the drain line DL, the voltage drop in the common line CL which serves as the power source line is more significant than in other lines. Hence, in the conventional image display apparatus, voltages supplied to the OLED 6 (i.e., the voltage levels of the common signals) varies significantly according to the difference in the length of the common lines CL from the common driver 5 (i.e., the difference in the amount of voltage drop), thereby causing the unevenness in luminance.
If the OLED 6 is located in the vicinity of the common driver 5, the common line CL extending from the common driver 5 to the OLED 6 is short in length. Then, the voltage drop along the common line CL is small and a predetermined voltage can be supplied to the OLED 6, resulting in the emission of light with a predetermined luminance. On the other hand, if the OLED 6 is far from the common driver 5, the common line CL extending from the common driver 5 to the OLED 6 is long in length. Then, the voltage drop is large and only a low level voltage is supplied to the OLED 6, resulting in light emission with a decreased luminance.
In addition, in the conventional image display apparatus, three drivers are separately arranged, i.e., the gate driver and the drain driver 4 that are related with the control lines (the gate line GL and the drain line DL), and the common driver 5 which is related with the power source line (the common line CL). Thus, requirement of space saving is hardly satisfied.